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1997 data sheet m pd703003 mos integrated circuit the m pd703003 is a member of the v850 family tm of 32-bit single-chip microcontrollers designed for real-time control operations. this microcontroller provides on-chip features, including a 32-bit cpu core, rom, ram, interrupt controller, real-time pulse unit, a serial interface, an a/d converter, a d/a converter, and pwm signal units. see the following manuals for a detailed description of this products functions. be sure to use these manuals as a reference for design. v853 users manual, hardware: u10913e v850 family users manual, architecture: u10243e features ? number of instructions: 74 ? minimum instruction execution time 30 ns (during 33-mhz operation) ? general registers 32 bits 32 registers ? instruction set optimized for control applications ? on-chip memory rom: 128 kbytes ram: 4 kbytes ? advanced on-chip interrupt controller ? real-time pulse unit suitable for control operations ? powerful serial interface (on-chip dedicated baud rate generator) ? on-chip clock generator ? 10-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? 8/9/10/12-bit resolution pwm: 2 channels ? power saving functions applications ? av: video cameras, vcrs, etc. ? office equipment: ppcs, lbps, printers, etc. ? industrial equipment: motor controllers, nc machine tools, etc. ? communications equipment: mobile telephones, etc. v853 tm 32/16-bit single-chip microcontroller the mark shows major revised points. document no. u12261ej2v1ds00 (2nd edition) date published april 1999 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd703003 2 data sheet u12261ej2v1ds00 ordering information part number package maximum operating frequency (mhz) m pd703003gc-25-xxx-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 25 m pd703003gc-33-xxx-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 33 remark xxx indicates rom code suffix. pin configuration ? 100-pin plastic qfp (fine pitch) (14 14 mm) m pd703003gc-25-xxx-7ea m pd703003gc-33-xxx-7ea caution connect the ic pin directly to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ano0 ano1 av ref2 av ref3 p07/intp113/adtrg p06/intp112 p05/intp111 p04/intp110 p03/ti11 p02/tclr11 p01/to111 p00/to110 p117/intp143 p116/intp142 p115/intp141 p114/intp140 p113/ti14 p112/tclr14 p111/to141 p31/to131 p32/tclr13 p33/ti13 p34/intp130 p35/intp131/so3 p36/intp132/si3 p37/intp133/sck3 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 v ss v dd p41/ad1 p40/ad0 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq wait ic mode reset cv dd /cksel x2 x1 cv ss clkout v ss v dd p110/to140 p30/to130 p27/sck1 p26/rxd1/si1 p25/txd1/so1 p24/sck0 p23/rxd0/si0 p22/txd0/so0 p21/pwm1 p20/pwm0 nmi v dd v ss p17/intp123/sck2 p16/intp122/si2 p15/intp121/so2 p14/intp120 p13/ti12 p12/tclr12 p11/to121 p10/to120 av dd av ss av ref1 p77/ani7 p76/ani6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
3 m pd703003 data sheet u12261ej2v1ds00 pin names a16 to a19 : address bus p30 to p37 : port3 ad0 to ad15 : address/data bus p40 to p47 : port4 adtrg : ad trigger input p50 to p57 : port5 ani0 to ani7 : analog input p60 to p63 : port6 ano0, ano1 : analog output p70 to p77 : port7 astb : address strobe p90 to p96 : port9 av dd : analog v dd p110 to p117 : port11 av ref1 to av ref3 : analog reference voltage pwm0, pwm1 : pulse width modulation av ss : analog v ss reset : reset cv dd : power supply for clock generator r/w : read/write status cv ss : ground for clock generator rxd0, rxd1 : receive data cksel : clock select sck0 to sck3 : serial clock clkout : clock output si0 to si3 : serial input dstb : data strobe so0 to so3 : serial output hldak : hold acknowledge to110, to111, : timer output hldrq : hold request to120, to121, ic : internally connected to130, to131, intp110 to intp113, : interrupt request from peripherals to140, to141 intp120 to intp123, tclr11 to tclr14 : timer clear intp130 to intp133, ti11 to ti14 : timer input intp140 to intp143 txd0, txd1 : transmit data lben : lower byte enable uben : upper byte enable mode : mode wait : wait nmi : non-maskable interrupt request x1, x2 : crystal p00 to p07 : port0 v dd : power supply p10 to p17 : port1 v ss : ground p20 to p27 : port2
m pd703003 4 data sheet u12261ej2v1ds00 internal block diagram nmi to110, to111 to120, to121 to130, to131 to140, to141 intp110 to intp113 intp120 to intp123 intp130 to intp133 intp140 to intp143 tclr11 to tclr14 ti11 to ti14 intc rpu sio mask rom ram 4 kbytes 128 kbytes cpu pc 32-bit barrel shifter system register general register 32 bits 32 alu multiplier 16 16 ? 32 port p110 to p117 p90 to p96 p70 to p77 p60 to p63 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 cg bcu instruction queue astb dstb r/w uben lben wait a16 to a19 ad0 to ad15 hldrq hldak clkout x1 x2 mode reset uart0/csi0 brg0 uart1/csi1 brg1 csi2 brg2 csi3 pwm so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 so2 si2 sck2 so3 si3 sck3 pwm0, pwm1 a/d converter ani0 to ani7 av ref1 av ss av dd adtrg d/a converter ano0, ano1 av ref2 , av ref3 v dd v ss cv dd cv ss cksel
5 m pd703003 data sheet u12261ej2v1ds00 contents 1. differences among products ........................................................................................... 6 2. list of pin functions ........................................................................................................ ....... 7 2.1 port pins ................................................................................................................... ............................. 7 2.2 non-port pins ............................................................................................................... ......................... 9 2.3 i/o circuits of pins and processing of unused pins ......................................................................... 1 1 3. function blocks .............................................................................................................. ......... 14 3.1 internal units .............................................................................................................. ........................... 14 4. cpu functions ................................................................................................................ ............ 16 5. bus control functions ........................................................................................................ .17 6. interrupt/exception handling functions ..................................................................... 18 7. clock generation functions .............................................................................................. 21 8. timer/counter functions (real-time pulse unit) ........................................................ 22 9. serial interface functions (sio) ....................................................................................... 24 9.1 asynchronous serial interface 0, 1 (uart0, uart1) ........................................................................ 24 9.2 clock-synchronized serial interface 0 to 3 (csi0 to csi3) ................................................................ 26 9.3 baud rate generator 0 to 2 (brg0 to brg2) ................................................................................... .. 28 10. pwm unit .................................................................................................................... ................... 29 11. a/d converter ............................................................................................................... ............. 30 12. d/a converter ............................................................................................................... ............. 31 13. port functions .............................................................................................................. ............ 32 14. reset functions ............................................................................................................. ........... 45 15. instruction set ............................................................................................................. ............ 46 16. electrical specifications ................................................................................................... .53 17. package drawings ............................................................................................................ ....... 77 18. recommended soldering conditions ............................................................................... 78
m pd703003 6 data sheet u12261ej2v1ds00 1. differences among products item m pd703003 m pd703003a m pd703004a m pd703025a m pd70f3003 m pd70f3003a m pd70f3025a internal rom mask rom flash memory 128 kbytes 96 kbytes 256 kbytes 128 kbytes 256 kbytes internal ram 4 kbytes 8 kbytes 4 kbytes 8 kbytes operation normal single-chip implemented mode operation mode mode rom-less implemented not implemented implemented not implemented mode flash memory not implemented implemented programming mode v pp pin not implemented implemented value of ckc register when reset 00h mode = 0 : 03h 00h mode = 0 : 03h mode = 1 : 00h mode = 1 : 00h electrical specifications power consumption levels vary (see specific products data sheet). others noise tolerance and noise emission vary, depending on the circuit scale and mask layout.
7 m pd703003 data sheet u12261ej2v1ds00 2. list of pin functions 2.1 port pins (1/2) pin name i/o function alternate function pin p00 i/o port 0 to110 p01 8-bit i/o port to111 p02 input/output mode can be specified bitwise tclr11 p03 ti11 p04 intp110 p05 intp111 p06 intp112 p07 intp113/adtrg p10 i/o port 1 to120 p11 8-bit i/o port to121 p12 input/output mode can be specified bitwise tclr12 p13 ti12 p14 intp120 p15 intp121/so2 p16 intp122/si2 p17 intp123/sck2 p20 i/o port 2 pwm0 p21 8-bit i/o port pwm1 p22 input/output mode can be specified bitwise txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 sck1 p30 i/o port 3 to130 p31 8-bit i/o port to131 p32 input/output mode can be specified bitwise tclr13 p33 ti13 p34 intp130 p35 intp131/so3 p36 intp132/si3 p37 intp133/sck3 p40 to p47 i/o port 4 ad0 to ad7 8-bit i/o port input/output mode can be specified bitwise p50 to p57 i/o port 5 ad8 to ad15 8-bit i/o port input/output mode can be specified bitwise
m pd703003 8 data sheet u12261ej2v1ds00 (2/2) pin name i/o function alternate function pin p60 to p63 i/o port 6 a16 to a19 4-bit i/o port input/output mode can be specified bitwise p70 to p77 input port 7 ani0 to ani7 8-bit input port p90 i/o port 9 lben p91 7-bit i/o port uben p92 input/output mode can be specified bitwise r/w p93 dstb p94 astb p95 hldak p96 hldrq p110 i/o port 11 to140 p111 8-bit i/o port to141 p112 input/output mode can be specified bitwise tclr14 p113 ti14 p114 intp140 p115 intp141 p116 intp142 p117 intp143
9 m pd703003 data sheet u12261ej2v1ds00 2.2 non-port pins (1/2) pin name i/o function alternate function pin to110 output pulse signal output from timers 11 to 14 p00 to111 p01 to120 p10 to121 p11 to130 p30 to131 p31 to140 p110 to141 p111 tclr11 input external clear signal input for timers 11 to 14 p02 tclr12 p12 tclr13 p32 tclr14 p112 ti11 input external count clock input for timers 11 to 14 p03 ti12 p13 ti13 p33 ti14 p113 intp110 input external maskable interrupt request input, p04 intp111 shared as external capture trigger input for timer 11 p05 intp112 p06 intp113 p07/adtrg intp120 input external maskable interrupt request input, p14 intp121 shared as external capture trigger input for timer 12 p15/so2 intp122 p16/si2 intp123 p17/sck2 intp130 input external maskable interrupt request input, p34 intp131 shared as external capture trigger input for timer 13 p35/so3 intp132 p36/si3 intp133 p37/sck3 intp140 input external maskable interrupt request input, p114 intp141 shared as external capture trigger input for timer 14 p115 intp142 p116 intp143 p117 so0 output serial transmit data output (3-wire) for csi0 to csi3 p22/txd0 so1 p25/txd1 so2 p15/intp121 so3 p35/intp131 si0 input serial receive data input (3-wire) for csi0 to csi3 p23/rxd0 si1 p26/rxd1 si2 p16/intp122 si3 p36/intp132
m pd703003 10 data sheet u12261ej2v1ds00 (2/2) pin name i/o function alternate function pin sck0 i/o serial clock i/o (3-wire) for csi0 to csi3 p24 sck1 p27 sck2 p17/intp123 sck3 p37/intp133 txd0 output serial transmit data output for uart0 and uart1 p22/so0 txd1 p25/so1 rxd0 input serial receive data input for uart0 and uart1 p23/si0 rxd1 p26/si1 pwm0 output pwm pulse signal output p20 pwm1 p21 ad0 to ad7 i/o 16-bit multiplexed address/data bus for external memory expansion p40 to p47 ad8 to ad15 p50 to p57 a16 to a19 output high-order address bus used for external memory expansion p60 to p63 lben output external data buss low-order byte enable signal output p90 uben external data buss high-order byte enable signal output p91 r/w output external read/write status output p92 dstb external data strobe signal output p93 astb external address strobe signal output p94 hldak output bus hold acknowledge output p95 hldrq input bus hold request input p96 ani0 to ani7 input analog input to a/d converter p70 to p77 ano0, ano1 output analog output to d/a converter nmi input nonmaskable interrupt request input clkout output system clock output cksel input input for specifying clock generators operation mode cv dd wait input control signal input for inserting wait in bus cycle mode input operation mode select reset input system reset input x1 input oscillator connection for system clock. input is via x1 when using an x2 external clock. adtrg input a/d converter external trigger input p07/intp113 av ref1 input reference voltage input for a/d converter av ref2 input reference voltage input for d/a converter av ref3 av dd positive power supply for a/d converter av ss ground potential for a/d converter cv dd positive power supply for on-chip clock generator cksel cv ss ground potential for on-chip clock generator v dd positive power supply v ss ground potential ic internally connected pin (connect directly to v ss )
11 m pd703003 data sheet u12261ej2v1ds00 2.3 i/o circuits of pins and processing of unused pins table 2-1 lists i/o circuit type of respective pins and processing method (recommended connection method) when not used. figure 2-1 illustrates the various circuit types using partially abridged diagrams. when connecting to v dd or v ss via a resistor, a resistance value in the range of 1 to 10 k w is recommended. table 2-1. i/o circuits of pins and processing of unused pins (1/2) pin i/o circuit type recommended connection method p00/to110, p01/to111 5 input: connect to v dd or v ss separately via a resistor p02/tclr11, p03/ti11, 8 output: leave open p04/intp110 to p07/intp113/adtrg p10/to120, p11/to121 5 p12/tclr12, p13/ti12 8 p14/intp120 p15/intp121/so2 p16/intp122/si2 p17/intp123/sck2 p20/pwm0, p21/pwm1 5 p22/txd0/so0 p23/rxd0/si0, p24/sck0 8 p25/txd1/so1 5 p26/rxd1/si1, p27/sck1 8 p30/to130, p31/to131 5 p32/tclr13, p33/ti13 8 p34/intp130 p35/intp131/so3 10-a p36/intp132/si3 p37/intp133/sck3 p40/ad0 to p47/ad7 5 p50/ad8 to p57/ad15 p60/a16 to p63/a19 p70/ani0 to p77/ani7 9 connect directly to v ss p90/lben 5 input: connect to v dd or v ss separately via a resistor p91/uben output: leave open p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq p110/to140, p111/to141 p112/tclr14, p113/ti14 8 p114/intp140 to p117/intp143 ano0, ano1 12 leave open nmi 2 connect directly to v ss
m pd703003 12 data sheet u12261ej2v1ds00 table 2-1. i/o circuits of pins and processing of unused pins (2/2) pin i/o circuit type recommended connection method clkout 3 leave open wait 1 connect directly to v dd mode 2 reset cv dd /cksel av ref1 to av ref3 , av ss connect directly to v ss av dd connect directly to v dd ic connect directly to v ss
13 m pd703003 data sheet u12261ej2v1ds00 figure 2-1. i/o circuits of pins type 1 type 2 type 8 type 3 p-ch n-ch in v dd in schmitt trigger input with hysteresis characteristics p-ch n-ch v dd out p-ch n-ch v dd in/out data output disable type 5 p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 data output disable p-ch in/out v dd n-ch p-ch v dd pull-up enable open-drain type 10-a out p-ch n-ch analog output voltage type 12
m pd703003 14 data sheet u12261ej2v1ds00 3. function blocks 3.1 internal units 3.1.1 cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as the multiplier (16 bits 16 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. 3.1.2 bus control unit (bcu) the bcu starts a required bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in a prefetch queue. 3.1.3 rom rom is mapped to the address space starting at 00000000h. the mode pin can be used to select an access enable/disable setting. rom can be accessed by the cpu in one clock cycle when an instruction is fetched. 3.1.4 ram ram is mapped to the address space starting at ffffe000h. ram can be accessed by the cpu in one clock cycle when data accessed. 3.1.5 ports in addition to the 75 pins (port 0 to port 11) comprising i/o ports (of which eight pins comprise an input-only port), various port pin and control pin functions can be selected for these pins. 3.1.6 interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp110 to intp113, intp120 to intp123, intp130 to intp133, and intp140 to intp143) from on-chip peripheral hardware and external hardware. eight interrupt priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. 3.1.7 clock generator (cg) an on-chip pll enables the cpu operating clock to be supplied to resonators connected to pins x1 and x2 at 5 frequency, 1 frequency, and 1/2 frequency. it can also be connected to an external clock instead of to the resonator. 3.1.8 real-time pulse unit (rpu) the rpu includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables measurement of pulse intervals and frequency as well as programmable pulse output.
15 m pd703003 data sheet u12261ej2v1ds00 3.1.9 serial interface (sio) four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (uart) and a clock- synchronized serial interface (csi). two of these four channels are switchable between the uart and csi and the other two channels are fixed as csi. for uart, data is transferred via the txd and rxd pins. the baud rate is determined by the on-chip baud rate generator. for csi, data is transferred via the so, si, and sck pins. the baud rate can be determined by the on- chip baud rate generator or it can be supplied from an external source. one of the two csi-fixed channels is used as the serial clock output, and serial output is sent via an n-ch open drain output. 3.1.10 pulse width modulation (pwm) there are two channels of selectable 8/9/10/12-bit resolution pwm signal outputs. when a low pass filter is externally connected, pwm output can be used as d/a converter output. this is suitable for actuator control applications, such as in motors. 3.1.11 a/d converter (adc) this is a high-speed, high-resolution 10-bit a/d converter that includes eight analog input pins. it converts using the sequential conversion method. 3.1.12 d/a converter (dac) this is an 8-bit resolution d/a converter that includes two channels. it converts using the r-2r conversion method.
m pd703003 16 data sheet u12261ej2v1ds00 4. cpu functions the cpu employs a risc-based architecture and uses five-stage pipeline control to enable single-clock execution of almost all instructions. the features of the cpu functions are shown below. ? minimum instruction execution time 30 ns (during internal 33-mhz operation) ? address space: 16-mbyte linear ? general registers: 32 bits 32 registers ? internal 32-bit architecture ? 5-stage pipeline control ? multiply/divide instructions ? saturated operation instructions ? 32-bit shift instruction: 1 clock ? long/short format ? four types of bit manipulation instructions ? set ? clear ? not ? test
17 m pd703003 data sheet u12261ej2v1ds00 5. bus control functions the features of the bus control functions are shown below. ? shared as port pins, connectable to external device ? wait functions ? programmable wait function for up to three states per two blocks ? external wait function using wait pin ? idle state insertion function ? bus mastering arbitration function ? bus hold function
m pd703003 18 data sheet u12261ej2v1ds00 6. interrupt/exception handling functions the features of the interrupt/exception handling functions are shown below. ? interrupts ? nonmaskable interrupt: 1 source ? maskable interrupt: 32 sources ? 8-level programmable priority control ? multiple interrupt control based on priority levels ? mask specification for each maskable interrupt request ? noise elimination, edge detection, and valid edge specification for external interrupt requests ? exceptions ? software exceptions: 32 sources ? exception trap: 1 source (invalid instruction code exception) the configuration of the interrupt/exception handling functions is shown below. figure 6-1. block diagram of maskable interrupt rpu selector 3210321032103210 3210 3210321032103210 321032103210 intm1 intm2 intm3 intm4 sio intcsi0 intov11 internal bus xxmkn (interrupt mask flag) ispr handler address generator cpu psw id interrupt request interrupt request acknowledge halt mode release signal xxprn (priority controller) 70 ovif11 ovif12 ovif13 ovif14 p11if0 p11if1 p11if2 p11if3 p12if0 p12if1 p12if2 p12if3 p13if0 p13if1 p13if2 p13if3 p14if0 p14if1 p14if2 p14if3 csif0 csif1 csif2 csif3 seif0 srif0 stif0 seif1 srif1 stif1 adif cmif4 intov12 intov13 intov14 intp110/intcc110 intp111/intcc111 intp112/intcc112 intp113/intcc113 intp120/intcc120 intp121/intcc121 intp122/intcc122 intp123/intcc123 intp130/intcc130 intp131/intcc131 intp132/intcc132 intp133/intcc133 intp140/intcc140 intp141/intcc141 intp142/intcc142 intp143/intcc143 intcm4 intad intcsi1 intcsi2 intcsi3 intser0 intsr0 intst0 intser1 intsr1 intst1 a/d converter intp110 intp111 intp112 intp113 intp120 intp121 intp122 intp123 intp130 intp131 intp132 intp133 intp140 intp141 intp142 intp143 xx: name of peripheral unit (ov, p11 to p14, cm, cs, se, sr, st, ad) n: peripheral unit number (if none exists, then 0 to 4 or 11 to 14)
19 m pd703003 data sheet u12261ej2v1ds00 interrupt/exception sources are shown in table 6-1. table 6-1. list of interrupts (1/2) interrupt/exception source default exception handler restored type category name control trigger source unit priority register level code address pc reset interrupt reset reset input 0000h 00000000h undefined nonmaskable interrupt nmi nmi input 0010h 00000010h nextpc software exception trap0n note trap instruction 004nh note 00000040h nextpc exception exception trap1n note trap instruction 005nh note 00000050h nextpc exception trap exception ilgop undefined instruction code 0060h 00000060h nextpc maskable interrupt intov11 ovic11 timer 11 overflow rpu 0 0080h 00000080h nextpc interrupt intov12 ovic12 timer 12 overflow rpu 1 0090h 00000090h nextpc interrupt intov13 ovic13 timer 13 overflow rpu 2 00a0h 000000a0h nextpc interrupt intov14 ovic14 timer 14 overflow rpu 3 00b0h 000000b0h nextpc interrupt intp110/intcc110 p11ic0 match between intp110 and cc110 pin/rpu 4 00c0h 000000c0h nextpc interrupt intp111/intcc111 p11ic1 match between intp111 and cc111 pin/rpu 5 00d0h 000000d0h nextpc interrupt intp112/intcc112 p11ic2 match between intp112 and cc112 pin/rpu 6 00e0h 000000e0h nextpc interrupt intp113/intcc113 p11ic3 match between intp113 and cc113 pin/rpu 7 00f0h 000000f0h nextpc interrupt intp120/intcc120 p12ic0 match between intp120 and cc120 pin/rpu 8 0100h 00000100h nextpc interrupt intp121/intcc121 p12ic1 match between intp121 and cc121 pin/rpu 9 0110h 00000110h nextpc interrupt intp122/intcc122 p12ic2 match between intp122 and cc122 pin/rpu 10 0120h 00000120h nextpc interrupt intp123/intcc123 p12ic3 match between intp123 and cc123 pin/rpu 11 0130h 00000130h nextpc interrupt intp130/intcc130 p13ic0 match between intp130 and cc130 pin/rpu 12 0140h 00000140h nextpc interrupt intp131/intcc131 p13ic1 match between intp131 and cc131 pin/rpu 13 0150h 00000150h nextpc interrupt intp132/intcc132 p13ic2 match between intp132 and cc132 pin/rpu 14 0160h 00000160h nextpc interrupt intp133/intcc133 p13ic3 match between intp133 and cc133 pin/rpu 15 0170h 00000170h nextpc interrupt intp140/intcc140 p14ic0 match between intp140 and cc140 pin/rpu 16 0180h 00000180h nextpc interrupt intp141/intcc141 p14ic1 match between intp141 and cc141 pin/rpu 17 0190h 00000190h nextpc interrupt intp142/intcc142 p14ic2 match between intp142 and cc142 pin/rpu 18 01a0h 000001a0h nextpc interrupt intp143/intcc143 p14ic3 match between intp143 and cc143 pin/rpu 19 01b0h 000001b0h nextpc interrupt intcm4 cmic4 signal matches cm4 rpu 20 01c0h 000001c0h nextpc interrupt intcsi0 csic0 csi0 send/receive completion sio 21 01d0h 000001d0h nextpc interrupt intcsi1 csic1 csi1 send/receive completion sio 22 01e0h 000001e0h nextpc interrupt intcsi2 csic2 csi2 send/receive completion sio 23 01f0h 000001f0h nextpc note n represents a value between 0 and fh. remarks 1. default priority: the default priority level is the level that takes precedence when multiple maskable interrupt requests having the same priority level occur at the same time. the highest priority level is level 0. restored pc: this is the pc value that is saved to eipc or fepc when interrupt or exception handling is activated. however, if an interrupt occurs during execution of the divh (divide) instruction, the recovered pc value is the pc value of the current instruction (divh). 2. the invalid instruction execution address can be obtained (using restored pc-4) when an invalid instruction code exception occurs.
m pd703003 20 data sheet u12261ej2v1ds00 table 6-1. list of interrupts (2/2) interrupt/exception source default exception handler restored type category name control trigger source unit priority register level code address pc maskable interrupt intcsi3 csic3 csi3 transmit/receive completion sio 24 0200h 00000200h nextpc interrupt intser0 seic0 uart0 receive error sio 25 0210h 00000210h nextpc interrupt intsr0 sric0 uart0 receive completion sio 26 0220h 00000220h nextpc interrupt intst0 stic0 uart0 transmit completion sio 27 0230h 00000230h nextpc interrupt intser1 seic1 uart1 receive error sio 28 0240h 00000240h nextpc interrupt intsr1 sric1 uart1 receive completion sio 29 0250h 00000250h nextpc interrupt intst1 stic1 uart1 transmit completion sio 30 0260h 00000260h nextpc interrupt intad adic a/d conversion completion adc 31 0270h 00000270h nextpc remarks 1. default priority: the default priority level is the level that takes precedence when multiple maskable interrupt requests having the same priority level occur at the same time. the highest priority level is level 0. restored pc: this is the pc value that is saved to eipc or fepc when interrupt or exception handling is started. however, if an interrupt occurs during execution of the divh (divide) instruction, the restored pc value is the pc value of the current instruction (divh). 2. the invalid instruction execution address can be obtained using (restored pc-4) when an invalid instruction code exception occurs.
21 m pd703003 data sheet u12261ej2v1ds00 7. clock generation functions the features of the clock generation functions are shown below. ? multiplier function using pll clock synthesizer ? clock sources ? oscillation via resonator connection (pll mode): f xx = f , 2 f , f /5 ? external clock (pll mode): f xx = f , 2 f , f /5 ? external clock (direct mode): f xx = 2 f ? power saving control ? halt mode ? idle mode ? software stop mode ? clock output inhibit mode the configuration of the clock generation functions is shown below. figure 7-1. block diagram of clock generation functions x1 x2 cksel (f xx ) clkout cpu, on-chip peripheral i/o clock generator f remark f : internal system clock
m pd703003 22 data sheet u12261ej2v1ds00 8. timer/counter functions (real-time pulse unit) the features of the timer/counter functions are shown below. ? measurement of pulse interval and frequency, programmable pulse output ? 16-bit measurements enabled ? generates a variety of pulse patterns (interval pulse, one-shot pulse, etc.) ? timer 1 ? 16-bit timer/event counter ? count clock sources: two types (selection of an internal system clock division, external pulse input) ? capture/compare (shared) registers: 16 ? count clear pins: tclr11 to tclr14 ? interrupt sources: 20 types ? external pulse outputs: 8 ? timer 4 ? 16-bit interval timer ? count clock: selected from an internal system clock division ? compare register: 1 ? interrupt sources: 1
23 m pd703003 data sheet u12261ej2v1ds00 the configurations of the timer/counter functions are shown below. figure 8-1. block diagram of timer 1 (16-bit timer/event counter) notes 1. internal count clock 2. external count clock 3. priority to reset remark f : internal system clock n = 1 to 4 figure 8-2. block diagram of timer 4 (16-bit interval timer) note internal count clock remark f : internal system clock m m/4 m/8 m/32 f f f f /2 /4 f f m f tclr1n ti1n intp1n0 intp1n1 intp1n2 intp1n3 note 2 note 1 clear and start tm1n (16 bits) cc1n0 cc1n1 cc1n2 cc1n3 intov1n intcc1n0 intcc1n1 s r note3 q q s q q r note3 intcc1n2 intcc1n3 to1n0 to1n1 edge detect clear and start edge detect edge detect edge detect edge detect edge detect tm4 (16-bit) cm4 clear and start intcm4 note m m/32 f f m f /2 /4 /16 /32 f f f f
m pd703003 24 data sheet u12261ej2v1ds00 9. serial interface functions (sio) two types and six channels of serial interfaces are provided. up to four channels may be used at the same time. (1) asynchronous serial interfaces 0, 1 (uart0, uart1): 2 channels (2) clock-synchronized serial interfaces 0 to 3 (csi0 to csi3): 4 channels caution uart0 and csi0 are a shared pin, as are uart1 and csi1. either one can be selected via a register (asim00, asim10). 9.1 asynchronous serial interfaces 0, 1 (uart0, uart1) the features of the asynchronous serial interfaces 0, 1 (uart0, uart1) are shown below. ? transfer rate 150 bps to 76800 bps (@ f = 33-mhz operation, using baud rate generator) 110 bps to 307200 bps (@ f = 20-mhz operation, using baud rate generator) maximum 1031 kbytes (@ f = 33-mhz operation, using f /2) ? full duplex communications: receive buffer (rxbn) included ? two-pin configuration txdn: output pin for transmit data rxdn: input pin for receive data ? reception error detection function ? parity error ? framing error ? overrun error ? three types of interrupt sources ? reception error interrupt (intsern) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) ? the character length of transmit and receive data is specified via the asimn0, asimn1 register ? character lengths: 7 or 8 bits, or 9 bits (if using expansion bit) ? parity function: even, odd, zero, or no parity ? transmission stop bits: 1 or 2 bits ? on-chip baud rate generator remark n = 0, 1 f : internal system clock
25 m pd703003 data sheet u12261ej2v1ds00 the configuration of the asynchronous serial interfaces 0, 1 (uart0, uart1) are shown below. figure 9-1. block diagram of asynchronous serial interfaces 0, 1 (uart0, uart1) internal bus 16/8 receive buffer 8 rxbn rxbnl receive shift register transmit shift register rxdn txdn reception control parity check transmission control parity attachment 1 16 intsrn intsern pen fen oven sotn asisn 16/8 txsn txsnl intstn selector 1 16 1 2 baud rate generator 88 asimn0 asimn1 ebsn rxen txen psn1 psn0 cln sln sclsn f remark n = 0, 1 f : internal system clock
m pd703003 26 data sheet u12261ej2v1ds00 9.2 clock-synchronized serial interfaces 0 to 3 (csi0 to csi3) the features of the clock-synchronized serial interfaces 0 to 3 (csi0 to csi3) are shown below. ? number of channels: 4 channels (csin) ? high-speed transfer max 8.25 mbps (@ f = 33-mhz operation) ? half-duplex communications ? character length uses 8-bit unit ? switchable byte ordering (msb first or lsb first) ? selectable external serial clock input/internal serial clock output ? 3-wire type son: serial data output sin: serial data input sckn: serial clock i/o ? interrupt source: 1 type ? transmission/reception completion interrupt (intcsin) remark n = 0 to 3 f : internal system clock
27 m pd703003 data sheet u12261ej2v1ds00 the configuration of the clock-synchronized serial interfaces 0 to 3 (csi0 to csi3) is shown below. figure 9-2. block diagram of clock-synchronized serial interfaces 0 to 3 (csi0 to csi3) note so0 to so2, sck0 to sck2: cmos outputs so3, sck3: n-ch open-drain outputs remark n = 0 to 3 f : internal system clock internal bus ctxen crxen csotn modn clsn1 clsn0 csimn sin son sckn shift register (sion) so latch dq 2 1 serial clock control circuit serial clock counter interrupt control circuit intcsin baud rate generator /2 note note selector selector f f
m pd703003 28 data sheet u12261ej2v1ds00 9.3 baud rate generators 0 to 2 (brg0 to brg2) the features of the baud rate generators 0 to 2 (brg0 to brg2) are shown below. ? serial clock can be selected via baud rate generator output and f (internal system clock) ? identical baud rates during transmission and reception the configuration of the baud rate generators 0 to 2 (brg0 to brg2) is shown below. figure 9-3. block diagram of baud rate generators 0 to 2 (brg0 to brg2) baud rate generator 0 baud rate generator 1 baud rate generator 2 internal bus 1 2 prescaler tmbrg0 clear brg0 match bprm0 brce0 bpr02 bpr01 bpr00 uart0 csi0 uart1 csi1 csi2 csi3 f
29 m pd703003 data sheet u12261ej2v1ds00 10. pwm unit the features of the pwm unit are shown below. ? pwmn: 2 channels ? selectable active level for pwmn output pulse ? operating clock selectable as f , f /2, f /4, f /8, or f /16 ( f : internal system clock) ? pwmn output resolution selectable as 8, 9, 10, or 12 bits remark n = 0, 1 the configuration of the pwm unit is shown below. figure 10-1. block diagram of pwm unit note priority to reset remark n = 0, 1 f : internal system clock tmpn (12 bits) comparator cmpn (12 bits) pwmn (12 bits) /2 /4 /8 /16 overflow match 7 8 9 11 0-7 0-8 0-9 0-11 sq r note alvn pwmn f f f f f
m pd703003 30 data sheet u12261ej2v1ds00 11. a/d converter the features of the a/d converter are shown below. ? analog inputs: 8 channels ? on-chip 10-bit a/d converter ? on-chip a/d conversion result registers (adcr0 to adcr7) 10 bits 8 registers ? a/d conversion trigger modes a/d trigger mode timer trigger mode external trigger mode ? sequential conversion method the configuration of the a/d converter is shown below. figure 11-1. block diagram of a/d converter internal bus ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intad controller adm0 (8) adm1 (8) 7 88 10 10 10 adcr0 sar (10) voltage comparator tap selector adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 7 00 0 9 0 r/2 series resistor string sample & hold circuit av ref1 av ss av dd r r/2 9 intcc110 intcc111 intcc112 noise elimination edge detection intcc113 adtrg input circuit
31 m pd703003 data sheet u12261ej2v1ds00 12. d/a converter the features of the d/a converter are shown below. ? 8-bit resolution d/a converter: 2 channels ? r-2r conversion method the configuration of the d/a converter is shown below. figure 12-1. block diagram of d/a converter remark n = 0, 1 dacsn selector dacen 2r 2r 2r 2r r r anon av ref2 av ref3 internal bus
m pd703003 32 data sheet u12261ej2v1ds00 13. port functions the features of the port functions are shown below. ? number of ports input-only ports: 8 i/o ports: 67 ? alternated as i/o pins for other peripheral functions ? i/o setting can be specified bitwise ? noise elimination ? edge detection the configurations of the port functions are shown below. figure 13-1. block diagram of p00 and p01 (port 0) remark n = 0, 1 wr pmc wr pm wr port rd in pmc0n internal bus pm0n p0n selector selector selector to11n p0n address
33 m pd703003 data sheet u12261ej2v1ds00 figure 13-2. block diagram of p02 to p07 (port 0) remark n = 2 to 7 figure 13-3. block diagram of p10 and p11 (port 1) remark n = 0, 1 wr pmc wr pm wr port rd in pmc0n internal bus pm0n p0n noise elimination edge detection p0n intp110-intp112, intp113/adtrg, tclr11, ti11 address selector selector wr pm wr port rd in pm1n to12n wr pmc pmc1n p1n p1n internal bus address selector selector selector
m pd703003 34 data sheet u12261ej2v1ds00 figure 13-4. block diagram of p12 to p14 (port 1) remark n = 2 to 4 figure 13-5. block diagram of p15 (port 1) pmc1n pm1n p1n rd in wr port wr pm wr pmc p1n tclr12, ti12 intp120 internal bus noise elimination edge detection address selector selector pmc15 pm15 p15 rd in wr port wr pm wr pmc p15 intp121 so2 pcm1 pcm1 internal bus noise elimination edge detection address selector selector selector
35 m pd703003 data sheet u12261ej2v1ds00 figure 13-6. block diagram of p16 (port 1) figure 13-7. block diagram of p17 (port 1) pmc16 pm16 p16 rd in wr port wr pm wr pmc p16 intp122 si2 pcm1 internal bus noise elimination edge detection address selector selector pmc17 pm17 p17 rd in wr port wr pm wr pmc p17 intp123 sck2 output pcm1 sck2 output sck2 i/o switch pcm1 internal bus noise elimination edge detection address selector selector selector
m pd703003 36 data sheet u12261ej2v1ds00 figure 13-8. block diagram of p20 and p21 (port 2) remark n = 0, 1 figure 13-9. block diagram of p22 and p25 (port 2) remark n = 2, 5 pmc2n pm2n p2n rd in wr port wr pm wr pmc pwm0, pwm1 p2n internal bus address selector selector selector pmc2n pm2n p2n rd in wr port wr pm wr pmc txd0/so0 txd1/so1 p2n so0, so1 output enable internal bus address selector selector selector
37 m pd703003 data sheet u12261ej2v1ds00 figure 13-10. block diagram of p23 and p26 (port 2) remark n = 3, 6 figure 13-11. block diagram of p24 and p27 (port 2) remark n = 4, 7 pmc2n pm2n p2n rd in wr port wr pm wr pmc p2n rxd0/si0 rxd1/si1 internal bus address selector selector pmc2n pm2n p2n rd in wr port wr pm wr pmc p2n sck0 input sck1 input sck0 output sck1 output sck0, sck1 i/o switch internal bus address selector selector selector
m pd703003 38 data sheet u12261ej2v1ds00 figure 13-12. block diagram of p30 and p31 (port 3) remark n = 0, 1 figure 13-13. block diagram of p32 to p34 (port 3) remark n = 2 to 4 wr pmc wr pm wr port rd in pmc3n pm3n p3n to13n p3n internal bus address selector selector selector pmc3n pm3n p3n rd in wr port wr pm wr pmc p3n tclr13, ti13 intp130 internal bus noise elimination edge detection address selector selector
39 m pd703003 data sheet u12261ej2v1ds00 figure 13-14. block diagram of p35 (port 3) figure 13-15. block diagram of p36 (port 3) pmc35 pm35 p35 rd in wr port wr pm wr pmc p35 intp131 pcm3 so3 so3 output enable pcm3 puo3 v dd p n p internal bus noise elimination edge detection address selector selector selector pmc36 pm36 p36 rd in wr port wr pm wr pmc p36 intp132 pcm3 puo3 v dd p n si3 p internal bus noise elimination edge detection address selector selector
m pd703003 40 data sheet u12261ej2v1ds00 figure 13-16. block diagram of p37 (port 3) figure 13-17. block diagram of p40 to p47 (port 4) remark n = 0 to 7 pmc37 pm37 p37 rd in wr port wr pm wr pmc p37 intp133 pcm3 puo3 v dd p n sck3 input sck3 output p sck3 i/o switch pcm3 internal bus noise elimination edge detection address selector selector selector pm4n p4n rd in wr port wr pm ad0 to ad7 output p4n ad0 to ad7 input i/o control circuit mode mm0 to mm2 internal bus address selector selector selector
41 m pd703003 data sheet u12261ej2v1ds00 figure 13-18. block diagram of p50 to p57 (port 5) remark n = 0 to 7 figure 13-19. block diagram of p60 to p63 (port 6) remark n = 0 to 3 pm5n p5n rd in wr port wr pm p5n i/o control circuit mode mm0 to mm2 ad8 to ad15 output ad8 to ad15 input internal bus address selector selector selector pm6n p6n rd in wr port wr pm a16 to a19 output p6n mode mm0 to mm2 i/o control circuit internal bus address selector selector selector
m pd703003 42 data sheet u12261ej2v1ds00 figure 13-20. block diagram of p70 to p77 (port 7) remark n = 0 to 7 figure 13-21. block diagram of p90 to p95 (port 9) remark n = 0 to 5 rd in p7n ani0 to ani7 sample & hold circuit internal bus pm9n p9n rd in wr port wr pm lben, uben, r/w, dstb, astb, hldak p9n mode mm0 to mm3 internal bus address selector selector selector i/o control circuit
43 m pd703003 data sheet u12261ej2v1ds00 figure 13-22. block diagram of p96 (port 9) figure 13-23. block diagram of p110 and p111 (port 11) remark n = 0, 1 pm96 p96 rd in wr port wr pm p96 mm3 hldrq i/o control circuit internal bus address selector selector wr pmc wr pm wr port rd in pmc11n pm11n p11n to14n p11n internal bus address selector selector selector
m pd703003 44 data sheet u12261ej2v1ds00 figure 13-24. block diagram of p112 to p117 (port 11) remark n = 2 to 7 pmc11n pm11n p11n rd in wr port wr pm wr pmc p11n tclr14, ti14 intp140 to intp143 internal bus noise elimination edge detection selector selector address
45 m pd703003 data sheet u12261ej2v1ds00 14. reset functions when low-level input occurs at the reset pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. when the input at the reset pin changes from low level to high level, the reset status is canceled and the cpu resumes program execution. the contents of the various registers should be initialized within the program as necessary. the feature of the reset functions is shown below. ? on-chip noise elimination circuit which uses analog delay ( @ 60 ns) for the reset pin
m pd703003 46 data sheet u12261ej2v1ds00 15. instruction set ? how to read instruction set tables table 15-1. symbols used to indicate operands symbol description reg1 general registers (r0 to r31): used as source registers reg2 general registers (r0 to r31): mainly used as destination registers ep element pointer (r30) bit#3 3-bit data used to specify bit number immx x bits immediate dispx x bits displaced regid system register number vector 5-bit data used to specify trap vector (00h to 1fh) cccc 4-bit data used to indicate condition code indicates the instruction group. instructions are listed in these table according to their respective groups. indicates the mnemonic abbreviation for the instruction. indicates the instruction's operands (see table 15-1 ). indicates the instruction binary code. the binary codes for 32-bit instructions are shown in two levels (see table 15-2 ). indicates instruction operation (see table 15-3 ). indicates flag operations (see table 15-4 ). mnemonic operand opcode operation flags cy ov s z sat instruction group
47 m pd703003 data sheet u12261ej2v1ds00 table 15-2. symbols used to indicate opcodes symbol description r 1-bit data of code specifying reg1 or regid r 1-bit data of code specifying reg2 d 1 bit of displaced data i 1 bit of immediate data cccc 4-bit data used to indicate condition code bbb 3-bit data used to specify bit number table 15-3. symbols used to indicate operations symbol description ? assign gr [ ] general register sr [ ] system register zero-extend (n) zero-extend n up until word length sign-extend (n) sign-extend n up until word length load-memory (a, b) read data having size b from address a store-memory (a, b, c) replace data b at address a with data having size c load-memory-bit (a, b) read bit b from address a store-memory-bit (a, b, c) write c to bit b from address a saturated (n) execute saturation processing for n (n = complement to 2) calculation of n: when n 3 7fffffffh, result is 7fffffffh. when n 80000000h, result is 80000000h. result result is indicated by flag operations byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + add C subtract || bit linkage multiply ? divide and logical and or logical or xor exclusive or not logical not logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right
m pd703003 48 data sheet u12261ej2v1ds00 table 15-4. flag operations identifier description (blank) no change 0 clear to zero set or clear according to result r restore previously saved value(s) table 15-5. condition codes condition name (cond) condition code (cccc) conditional expression description v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 C always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ((s xor ov) or z) = 1 less than or equal signed gt 1111 ((s xor ov) or z) = 0 greater than signed
49 m pd703003 data sheet u12261ej2v1ds00 instruction set list instruction mnemonic operand opcode operation flags group cy ov sz sat load/store sld.b disp7[ep], reg2 r r r r r 0110ddddddd adr ? ep + zero-extend (disp7) instructions gr[reg2] ? sign-extend (load-memory (adr, byte)) sld.h disp8[ep], reg2 r r r r r 1000ddddddd adr ? ep + zero-extend (disp8) note 1 gr[reg2] ? sign-extend (load-memory (adr, halfword)) sld.w disp8[ep], reg2 r r r r r 1010dddddd0 adr ? ep + zero-extend (disp8) note 2 gr[reg2] ? load-memory (adr, word) ld.b disp16[reg1], reg2 r r r r r 111000rrrrr adr ? gr[reg1] + sign-extend (disp16) dddddddddddddddd gr[reg2] ? sign-extend (load-memory (adr, byte)) ld.h disp16[reg1], reg2 r r r r r 111001rrrrr adr ? gr[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 gr[reg2] ? sign-extend (load-memory (adr, halfword)) note 3 ld.w disp16[reg1], reg2 r r r r r 111001rrrrr adr ? gr[reg1] + sign-extend (disp16) ddddddddddddddd1 gr[reg2] ? load-memory (adr, word) note 3 sst.b reg2, disp7[ep] r r r r r 0111ddddddd adr ? ep + zero-extend (disp7) store-memory (adr, gr[reg2], byte) sst.h reg2, disp8[ep] r r r r r 1001ddddddd adr ? ep + zero-extend (disp8) note 1 store-memory (adr, gr[reg2], halfword) sst.w reg2, disp8[ep] r r r r r 1010dddddd1 adr ? ep + zero-extend (disp8) note 2 store-memory (adr, gr[reg2], word) st.b reg2, disp16[reg1] r r r r r 111010rrrrr adr ? gr[reg1] + sign-extend (disp16) dddddddddddddddd store-memory (adr, gr[reg2], byte) st.h reg2, disp16[reg1] r r r r r 111011rrrrr adr ? gr[reg1] + sign-extend (disp16) ddddddddddddddd0 store-memory (adr, gr[reg2], halfword) note 3 st.w reg2, disp16[reg1] r r r r r 111011rrrrr adr ? gr[reg1] + sign-extend (disp16) ddddddddddddddd1 store-memory (adr, gr[reg2], word) note 3 arithmetic mov reg1, reg2 r r r r r 000000rrrrr gr[reg2] ? gr[reg1] operation mov imm5, reg2 r r r r r 010000 i i i i i gr[reg2] ? sign-extend (imm5) instructions movhi imm16, reg1, reg2 r r r r r 110010rrrrr gr[reg2] ? gr[reg1] + (imm16 || 0 16 ) iiiiiiiiiiiiiiii movea imm16, reg1, reg2 r r r r r 110001rrrrr gr[reg2] ? gr[reg1] + sign-extend (imm16) iiiiiiiiiiiiiiii add reg1, reg2 r r r r r 001110rrrrr gr[reg2] ? gr[reg2] + gr[reg1] add imm5, reg2 r r r r r 010010 i i i i i gr[reg2] ? gr[reg2] + sign-extend (imm5) addi imm16, reg1, reg2 r r r r r 110000rrrrr gr[reg2] ? gr[reg1] + sign-extend (imm16) iiiiiiiiiiiiiiii sub reg1, reg2 r r r r r 001101rrrrr gr[reg2] ? gr[reg2] C gr[reg1] subr reg1, reg2 r r r r r 001100rrrrr gr[reg2] ? gr[reg1] C gr[reg2] notes 1. ddddddd = high-order 7 bits of disp8 2. dddddd = high-order 6 bits of disp8 3. ddddddddddddddd = high-order 15 bits of disp16
m pd703003 50 data sheet u12261ej2v1ds00 instruction mnemonic operand opcode operation flags group cy ov sz sat arithmetic mulh reg1, reg2 r r r r r 0 0 0 1 1 1rrrrr gr[reg2] ? gr[reg2] note gr[reg1] note operation (signed multiplication) instructions mulh imm5, reg2 rrrrr010111i i i i i gr[reg2] ? gr[reg2] note sign-extend (imm5) (signed multiplication) mulhi imm16, reg1, reg2 r r r r r 1 1 0 1 1 1rrrrr gr[reg2] ? gr[reg1] note imm16 iiiiiiiiiiiiiiii (signed multiplication) divh reg1, reg2 r r r r r 0 0 0 0 1 0rrrrr gr[reg2] ? gr[reg2] ? gr[reg1] note (signed division) cmp reg1, reg2 r r r r r 0 0 1 1 1 1rrrrr result ? gr[reg2] C gr[reg1] cmp imm5, reg2 rrrrr010011i i i i i result ? gr[reg2] C sign-extend (imm5) setf cccc, reg2 r r r r r1111110cccc if conditions are satisfied 0000000000000000 then gr[reg2] ? 00000001h else gr[reg2] ? 00000000h saturated satadd reg1, reg2 r r r r r 0 0 0 1 1 0rrrrr gr[reg2] ? saturated (gr[reg2] + gr[reg1]) operation satadd imm5, reg2 r r r r r 0 1 0 0 0 1 i i i i i gr[reg2] ? saturated (gr[reg2] + sign-extend (imm5)) instructions satsub reg1, reg2 r r r r r 0 0 0 1 0 1rrrrr gr[reg2] ? saturated (gr[reg2] C gr[reg1]) satsubi imm16, reg1, reg2 r r r r r 1 1 0 0 1 1rrrrr gr[reg2] ? saturated (gr[reg1] C sign-extend (imm16)) iiiiiiiiiiiiiiii satsubr reg1, reg2 r r r r r 0 0 0 1 0 0rrrrr gr[reg2] ? saturated (gr[reg1] C gr[reg2]) logical tst reg1, reg2 r r r r r 0 0 1 0 1 1rrrrr result ? gr[reg2]and gr[reg1] 0 operation or reg1, reg2 r r r r r 0 0 1 0 0 0rrrrr gr[reg2] ? gr[reg2]or gr[reg1] 0 instruction ori imm16, reg1, reg2 r r r r r 1 1 0 1 0 0rrrrr gr[reg2] ? gr[reg1]or zero-extend (imm16) 0 iiiiiiiiiiiiiiii and reg1, reg2 r r r r r 0 0 1 0 1 0rrrrr gr[reg2] ? gr[reg2]and gr[reg1] 0 andi imm16, reg1, reg2 r r r r r 1 1 0 1 1 0rrrrr gr[reg2] ? gr[reg1]and zero-extend (imm16) 0 0 iiiiiiiiiiiiiiii xor reg1, reg2 r r r r r 0 0 1 0 0 1rrrrr gr[reg2] ? gr[reg2]xor gr[reg1] 0 xori imm16, reg1, reg2 r r r r r 1 1 0 1 0 1rrrrr gr[reg2] ? gr[reg1]xor zero-extend (imm16) 0 iiiiiiiiiiiiiiii not reg1, reg2 rrrrr00001rrrrr gr[reg2] ? not (gr[reg1]) 0 shl reg1, reg2 r r r r r 1 1 1 1 1 1rrrrr gr[reg2] ? gr[reg2]logically shift left by gr[reg1] 0 0000000011000000 shl imm5, reg2 rrrrr010110i i i i i gr[reg2] ? gr[reg2]logically shift left by 0 zero-extend (imm5) shr reg1, reg2 r r r r r 1 1 1 1 1 1rrrrr gr[reg2] ? gr[reg2]logically shift right by gr[reg1] 0 0000000010000000 shr imm5, reg2 rrrrr010100i i i i i gr[reg2] ? gr[reg2]logically shift right by 0 zero-extend (imm5) sar reg1, reg2 r r r r r 1 1 1 1 1 1rrrrr gr[reg2] ? gr[reg2]arithmetically shift right by 0 0000000010100000 gr[reg1] sar imm5, reg2 rrrrr010101i i i i i gr[reg2] ? gr[reg2]arithmetically shift right by 0 zero-extend (imm5) note only the low-order half word is valid.
51 m pd703003 data sheet u12261ej2v1ds00 instruction mnemonic operand opcode operation flags group cy ov sz sat branch jmp [reg1] 00000000011rrrrr pc ? gr[reg1] instructions jr disp22 0000011110dddddd pc ? pc + sign-extend (disp22) ddddddddddddddd0 note 1 jarl disp22, reg2 r r r r r 11110dddddd gr[reg2] ? pc + 4 ddddddddddddddd0 pc ? pc + sign-extend (disp22) note 1 bcond disp9 ddddd1011dddcccc if conditions are satisfied note 2 then pc ? pc + sign-extend (disp9) bit set1 bit#3, disp16[reg1] 00bbb111110rrrrr adr ? gr[reg1] + sign-extend (disp16) manipulation dddddddddddddddd z flag ? not (load-memory-bit (adr, bit#3)) instructions store-memory-bit (adr, bit#3, 1) clr1 bit#3, disp16[reg1] 10bbb111110rrrrr adr ? gr[reg1] + sign-extend (disp16) dddddddddddddddd z flag ? not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) not1 bit#3, disp16[reg1] 01bbb111110rrrrr adr ? gr[reg1] + sign-extend (disp16) dddddddddddddddd z flag ? not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) tst1 bit#3, disp16[reg1] 11bbb111110rrrrr adr ? gr[reg1] + sign-extend (disp16) dddddddddddddddd z flag ? not (load-memory-bit (adr, bit#3)) notes 1. ddddddddddddddddddddd = high-order 21 bits of disp22 2. dddddddd = high-order 8 bits of disp9
m pd703003 52 data sheet u12261ej2v1ds00 instruction mnemonic operand opcode operation flags group cy ov sz sat special ldsr reg2, regid r r r r r 1 1 1 1 1 1rrrrr sr[regid] ? gr[reg2] regid = eipc, fepc instructions 0000000000100000 regid = eipsw, fepsw note regid = psw stsr regid, reg2 r r r r r 1 1 1 1 1 1rrrrr gr[reg2] ? sr[regid] 0000000001000000 trap vector 00000111111 i i i i i eipc ? pc + 4 (restored pc) 0000000100000000 eipsw ? psw ecr.eicc ? interrupt code psw.ep ? 1 psw.id ? 1 pc ? 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) reti 0000011111100000 if psw.ep = 1 r r r r r 0000000101000000 then pc ? eipc psw ? eipsw else if psw.np = 1 then pc ? fepc psw ? fepsw else pc ? eipc psw ? eipsw halt 0000011111100000 stops 0000000100100000 di 0000011111100000 psw.id ? 1 0000000101100000 (maskable interrupt prohibit) ei 1000011111100000 psw.id ? 0 0000000101100000 (maskable interrupt enable) nop 0000000000000000 no operation, uses at least one clock note in this instructions, reg2 is the mnemonic abbreviation for the source register, but the reg1 field is used for the opcode. consequently, these instructions differ from other instructions in a way registers are specified in mnemonics description and opcodes. rrrrr = regid specification rrrrr = reg2 specification
53 m pd703003 data sheet u12261ej2v1ds00 16. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating units power supply voltage v dd v dd pin C0.5 to +7.0 v cv dd cv dd pin C0.5 to v dd + 0.3 v cv ss cv ss pin C0.5 to +0.5 v av dd av dd pin C0.5 to v dd + 0.3 v av ss av ss pin C0.5 to +0.5 v input voltage v i1 note , v dd = 5.0 v 10 % C0.5 to v dd + 0.3 v clock input voltage v k x1 pin, v dd = 5.0 v 10 % C0.5 to v dd + 1.0 v low-level output current i ol 1 pin 4.0 ma total for all pins 100 ma high-level output current i oh 1 pin C4.0 ma total for all pins C100 ma output voltage v o v dd = 5.0 v 10 % C0.5 to v dd + 0.3 v analog input voltage v ian p70/ani0 to p77/ani7 av dd > v dd C0.5 to v dd + 0.3 v v dd 3 av dd C0.5 to av dd + 0.3 v analog reference input voltage av ref av ref1 to av ref3 av dd > v dd C0.5 to v dd + 0.3 v v dd 3 av dd C0.5 to av dd + 0.3 v operating temperature t a C40 to +85 c storage temperature t stg C65 to +150 c note x1, p70/ani0 to p77/ani7, and av ref1 to av ref3 are excluded. cautions 1. be sure to avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, open-drain pins and open collector pins can be directly connected. a direct connection to an external circuit can be made to avoid conflicting output from high-impedance pins if the external circuit is designed for the correct timing. 2. if the absolute maximum rating for any of the above parameters is exceeded even momentarily, it may adversely affect the quality of this product. in other words, these absolute maximum ratings have been set to prevent physical damage to the product. do not use the product in such a way as to exceed any of these ratings. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. units input capacitance c i f c = 1 mhz 15 pf i/o capacitance c io all pins are 0 v except for testing pin. 15 pf output capacitance c o 15 pf
m pd703003 54 data sheet u12261ej2v1ds00 recommended operating conditions operation mode internal operating operating ambient power supply clock frequency ( f ) temperature (t a ) voltage (v dd ) direct mode 0 to 33 mhz note 1 C40 to +85 c 5.0 v 10% 5 to 33 mhz note 2 C40 to +85 c 5.0 v 10% pll mode free-running oscillation frequency to 33 mhz C40 to +85 c 5.0 v 10% notes 1. when not using a/d converter 2. when using a/d converter remark the range of internal operating clock frequency in pll mode is the assured range of function operation. pll locked frequency is specified by t cyx . recommended oscillator (a) ceramic oscillation resonator connection (t a = C40 to +85 c) x1 x2 c1 c2 oscillation recommended circuit oscillation voltage oscillation stabilization manufacturer part number frequency constant range time (max.) f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) t ost (ms) tdk ccr5.0mc3 5.0 on-chip on-chip 4.5 5.5 0.36 fcr5.0mc5 5.0 on-chip on-chip 4.5 5.5 0.32 ccr6.6mc3 6.6 on-chip on-chip 4.5 5.5 0.28 murata mfg. csa5.00mg040 5.0 100 100 4.5 5.5 0.46 cst5.00mgw040 5.0 on-chip on-chip 4.5 5.5 0.46 csa6.60mtz040 6.6 100 100 4.5 5.5 0.42 cst6.60mtw040 6.6 on-chip on-chip 4.5 5.5 0.42 cautions 1. set the oscillator as close to the x1 and x2 pins as possible. 2. no other signal lines should be wired in the area enclosed by broken lines. 3. when matching m pd703003 with a resonator, be sure to perform sufficient evaluation.
55 m pd703003 data sheet u12261ej2v1ds00 (b) external clock input x1 high-speed cmos inverter external clock x2 open cautions 1. set high-speed cmos inverter as close as possible to the x1 pin. 2. when matching m pd703003 and a high-speed cmos inverter, be sure to perform sufficient evaluation.
m pd703003 56 data sheet u12261ej2v1ds00 dc characteristics (t a = C40 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) (1/2) parameter symbol condition min. typ. max. units high-level input voltage v ih except for x1 and pins listed in note 2.2 v dd + 0.3 v note 0.8 v dd v dd + 0.3 v low-level input voltage v il except for x1 and pins listed in note C0.5 +0.8 v note C0.5 0.2 v dd v high-level clock input voltage v xh x1 0.8 v dd v dd + 0.5 v low-level clock input voltage v xl x1 C0.5 +0.6 v schmitt trigger input v t + note , rising edge 3.0 v threshold voltage v t C note , falling edge 2.0 v schmitt trigger input hysteresis width v t + C v t C note 0.5 v high-level output voltage v oh i oh = C2.5 ma 0.7 v dd v i oh = C100 m av dd C 0.5 v low-level output voltage v ol i ol = 2.5 ma 0.45 v high-level input leak current i lih v i = v dd 10 m a low-level input leak current i lil v i = 0 v C10 m a high-level output leak current i loh v o = v dd 10 m a low-level output leak current i lol v o = 0 v C10 m a software pull-up resistance r p35/intp131/so3, 15 40 90 k w p36/intp132/si3, p37/intp133/sck3 note p02/tclr11, p03/ti11, p04/intp110 to p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/ intp121/so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/ sck3, p112/tclr14, p113/ti14, p114/intp140 to p117/intp143, reset, nmi, mode remarks 1. typ. values are reference values for when t a = 25 c and v dd = 5.0 v. 2. f = internal system clock frequency
57 m pd703003 data sheet u12261ej2v1ds00 dc characteristics (t a = C40 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) (2/2) parameter symbol condition min. typ. max. units power supply current when i dd1 direct mode note 2.4 f + 6 2.8 f + 19 ma operating pll mode 2.5 f + 8 2.9 f + 22 ma during i dd2 direct mode note 1.4 f + 5 1.5 f + 18 ma halt mode pll mode 1.5 f + 7 1.6 f + 20 ma during i dd3 direct mode note 18.6 f + 100 22 f + 200 m a idle mode pll mode 0.05 f + 4 0.1 f + 8 ma during i dd4 C40 c t a +50 c250 m a stop mode 50 c < t a 85 c 2 200 m a note when using a/d converter: f = 5 to 33 mhz when not using a/d converter: f = 0 to 33 mhz remarks 1. typ. values are reference values for when t a = 25 c and v dd = 5.0 v. the power supply current does not include av ref1 to av ref3 or the current that flows across the software pull-up resistance. 2. f = internal system clock frequency
m pd703003 58 data sheet u12261ej2v1ds00 data hold characteristics (t a = C40 to +85 c) parameter symbol conditions min. typ. max. units data hold voltage v dddr stop mode 1.5 5.5 v data hold current i dddr v dd = v dddr C40 c t a +50 c 0.2 v dddr 50 m a 50 c < t a 85 c 0.2 v dddr 200 m a power supply voltage rise time t rvd 200 m s power supply voltage fall time t fvd 200 m s power supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode release signal input time t drel 0ns data hold high-level input voltage v ihdr note 0.9 v dddr v dddr v data hold low-level input voltage v ildr note 0 0.1 v dddr v note p02/tclr11, p03/ti11, p04/intp110 to p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/ intp121/so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/ sck3, p112/tclr14, p113/ti14, p114/intp140 to p117/intp143, reset, nmi, mode, x1 remark typ. values are reference values for when t a = 25 c and v dd = 5.0 v. t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (released at falling edge) v ihdr v ildr nmi (input) (released at rising edge) stop mode setting (fifth clock after psc register is set)
59 m pd703003 data sheet u12261ej2v1ds00 ac characteristics (t a = C40 to +85 c, v dd = 5 v 10%, v ss = 0 v) ac test input waveform (a) p02/tclr11, p03/ti11, p04/intp110 to p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/intp121/ so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, p32/ tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/sck3, p112/tclr14, p113/ti14, p114/intp140 to p117/intp143, reset, nmi, mode, x1 (b) pins other than those listed in (a) above ac test output test points load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the devices load capacitance to below 50 pf. test points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v test points 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v test points 2.2 v 0.8 v 2.2 v 0.8 v c l = 50 pf dut (device under testing)
m pd703003 60 data sheet u12261ej2v1ds00 (1) clock timing parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. x1 input cycle <1> t cyx direct mode 20 note 1 15 note 1 ns pll mode (pll locked) 200 250 150 250 ns x1 input high-level width <2> t wxh direct mode 7 6 ns pll mode 80 60 ns x1 input low-level width <3> t wxl direct mode 7 6 ns pll mode 80 60 ns x1 input rise time <4> t xr direct mode 7 7 ns pll mode 15 10 ns x1 input fall time <5> t xf direct mode 7 7 ns pll mode 15 10 ns cpu operating frequency f direct mode note 2 25 note 2 33 mhz pll mode note 3 25 note 3 33 mhz clkout output cycle <6> t cyk 40 note 4 30 note 4 ns clkout input high-level width <7> t wkh 0.5t C 5 0.5t C 5 ns clkout input low-level width <8> t wkl 0.5t C 5 0.5t C 5 ns clkout input rise time <9> t kr 55ns clkout input fall time <10> t kf 55ns x1 ? clkout delay time <11> t dxk direct mode 3 17 3 17 ns notes 1. when using a/d converter : 100 ns when not using a/d converter : dc 2. when using a/d converter : 5 mhz when not using a/d converter : 0 mhz 3. free-running oscillation frequency 4. when using a/d converter : 200 ns when not using a/d converter : dc remark t = t cyk parameter symbol conditions typ. units free-running oscillation frequency f p pll mode 5 mhz x1 (input) clkout (output) <1> <2> <4> <5> <6> <7> <11> <11> <8> <9> <10> <3>
61 m pd703003 data sheet u12261ej2v1ds00 (2) input waveform (a) p02/tclr11, p03/ti11, p04/intp110 to p07/intp113, p12/tclr12, p13/ti12, p14/intp120, p15/ intp121/so2, p16/intp122/si2, p17/intp123/sck2, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/ sck1, p32/tclr32, p33/ti13, p34/intp130, p35/intp131/so3, p36/intp132/si3, p37/intp133/ sck3, p112/tclr14, p113/ti14, p114/intp140 to p117/intp143, reset, nmi, mode parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. input rise time <12> t ir2 20 20 ns input fall time <13> t if2 20 20 ns (b) pins other than those listed in (a) above parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. input rise time <14> t ir1 10 10 ns input fall time <15> t if1 10 10 ns 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v <13> <12> input signal 2.2 v <15> <14> 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v input signal
m pd703003 62 data sheet u12261ej2v1ds00 (3) output waveform (other than clkout) parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. output rise time <16> t or 12 12 ns output fall time <17> t of 12 12 ns (4) reset timing parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. reset high-level width <18> t wrsh 500 500 ns reset low-level width <19> t wrsl when power supply is on 500 + t ost 500 + t ost ns and stop mode has been released other than when power 500 500 ns supply is on and stop mode has been released remark t ost : oscillation stabilization time 0.8 v <16> <17> 2.2 v 2.2 v 0.8 v output signal reset (input) <18> <19>
63 m pd703003 data sheet u12261ej2v1ds00 [memo]
m pd703003 64 data sheet u12261ej2v1ds00 (5) read timing (1/2) parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. clkout - ? address delay time <20> t dka 3 20 3 20 ns clkout - ? r/w, uben, lben delay time <78> t dka2 C2 +13 C2 +13 ns clkout - ? address float delay time <21> t fka 3 15 3 15 ns clkout ? astb delay time <22> t dkst C2 +13 C2 +13 ns clkout - ? dstb delay time <23> t dkd C2 +13 C2 +13 ns data input setup time (to clkout - ) <24> t sidk 77ns data input hold time (from clkout - ) <25> t hkid 55ns wait setup time (to clkout ) <26> t swtk 88ns wait hold time (from clkout ) <27> t hkwt 55ns address hold time (from clkout - ) <28> t hka 00ns address setup time (to astb ) <29> t sast 0.5t C 10 0.5t C 10 ns address hold time (from astb ) <30> t hsta 0.5t C 10 0.5t C 10 ns dstb ? address float delay time <31> t fda 00ns data input setup time (to address) <32> t said (2 + n)t C 20 (2 + n)t C 20 ns data input setup time (to dstb ) <33> t sdid (1 + n)t C 20 (1 + n)t C 20 ns astb ? dstb delay time <34> t dstd 0.5t C 10 0.5t C 10 ns data input hold time (from dstb - ) <35> t hdid 00ns dstb - ? address output delay time <36> t dda (1 + i)t C 3 (1 + i)t C 3 ns dstb - ? astb - delay time <37> t ddsth 0.5t C 10 0.5t C 10 ns dstb - ? astb delay time <38> t ddstl (1.5 + i)t C 10 (1.5 + i)t C 10 ns dstb low-level width <39> t wdl (1 + n)t C 10 (1 + n)t C 10 ns astb high-level width <40> t wsth t C 10 t C 10 ns wait setup time (to address) <41> t sawt1 n 3 1 1.5t C 20 1.5t C 20 ns <42> t sawt2 (1.5 + n)t C 20 (1.5 + n)t C 20 ns wait hold time (from address) <43> t hawt1 n 3 1 (0.5 + n)t (0.5 + n)t ns <44> t hawt2 (1.5 + n)t (1.5 + n)t ns wait setup time (to astb ) <45> t sstwt1 n 3 1 t C 15 t C 15 ns <46> t sstwt2 (1 + n)t C 15 (1 + n)t C 15 ns wait hold time (from astb ) <47> t hstwt1 n 3 1ntntns <48> t hstwt2 (1 + n)t (1 + n)t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. maintain at least one of the two data input hold times, either t hkid (<25>) or t hdid (<35>).
65 m pd703003 data sheet u12261ej2v1ds00 (5) read timing (2/2): 1 wait remark broken line indicates high impedance. t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0 to ad15 (i/o) astb (output) dstb (output) wait (input) <32> <20> r/w (output) uben (output) lben (output) <78> <28> <25> <24> <21> a0 to a15 (output) d0 to d15 (input) <22> <29> <30> <22> <35> <37> <36> <23> <31> <34> <40> <33> <23> <39> <38> <26> <27> <26> <47> <46> <48> <27> <45> <41> <44> <43> <42>
m pd703003 66 data sheet u12261ej2v1ds00 (6) write timing (1/2) parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. clkout - ? address delay time <20> t dka 3 20 3 20 ns clkout - ? r/w, uben, lben delay time <78> t dka2 C2 +13 C2 +13 ns clkout ? astb delay time <22> t dkst C2 +13 C2 +13 ns clkout - ? dstb delay time <23> t dkd C2 +13 C2 +13 ns wait setup time (to clkout ) <26> t swtk 88ns wait hold time (from clkout ) <27> t hkwt 55ns address hold time (from clkout - ) <28> t hka 00ns address setup time (to astb ) <29> t sast 0.5t C 10 0.5t C 10 ns address hold time (from astb ) <30> t hsta 0.5t C 10 0.5t C 10 ns astb ? dstb delay time <34> t dstd 0.5t C 10 0.5t C 10 ns dstb - ? astb - delay time <37> t ddsth 0.5t C 10 0.5t C 10 ns dstb low-level width <39> t wdl (1 + n)t C 10 (1 + n)t C 10 ns astb high-level width <40> t wsth t C 10 t C 10 ns wait setup time (to address) <41> t sawt1 n 3 1 1.5t C 20 1.5t C 20 ns <42> t sawt2 (1.5 + n)t C 20 (1.5 + n)t C 20 ns wait hold time (from address) <43> t hawt1 n 3 1 (0.5 + n)t (0.5 + n)t ns <44> t hawt2 (1.5 + n)t (1.5 + n)t ns wait setup time (to astb ) <45> t sstwt1 n 3 1 t C 15 t C 15 ns <46> t sstwt2 (1 + n)t C 15 (1 + n)t C 15 ns wait hold time (from astb ) <47> t hstwt1 n 3 1ntntns <48> t hstwt2 (1 + n)t (1 + n)t ns clkout - ? data output delay time <49> t dkod 20 20 ns dstb ? data output delay time <50> t ddod 10 10 ns data output hold time (from clkout - ) <51> t hkod 00ns data output setup time (to dstb - ) <52> t sodd (1 + n)t C 15 (1 + n)t C 15 ns data output hold time (from dstb - ) <53> t hdod t C 10 t C 10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function.
67 m pd703003 data sheet u12261ej2v1ds00 (6) write timing (2/2): 1 wait remark broken line indicates high impedance. t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0 to ad15 (i/o) astb (output) dstb (output) wait (input) <20> <78> <28> <49> a0 to a15 (output) d0 to d15 (output) <22> <29> <30> <22> <37> <53> <23> <50> <23> <40> <52> <34> <39> <26> <27> <26> <47> <46> <48> <27> <45> <41> <44> <43> <42> <51> r/w (output) uben (output) lben (output)
m pd703003 68 data sheet u12261ej2v1ds00 (7) bus hold timing (1/2) parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. hldrq setup time (to clkout ) <54> t shqk 88ns hldrq hold time (from clkout ) <55> t hkhq 55ns clkout - ? hldak delay time <56> t dkha 20 20 ns hldrq high-level width <57> t whqh t + 10 t + 10 ns hldak low-level width <58> t whal t C 10 t C 10 ns clkout - ? bus float delay time <59> t dkf 20 20 ns hldak - ? bus output delay time <60> t dhac C3 C3 ns hldrq ? hldak delay time <61> t dhqha1 (2n + 7.5)t + 20 (2n + 7.5)t + 20 ns hldrq - ? hldak - delay time <62> t dhqha2 0.5t 1.5t + 20 0.5t 1.5t + 20 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function.
69 m pd703003 data sheet u12261ej2v1ds00 (7) bus hold timing (2/2) th th th ti th clkout (output) a16 to a19 (output) note hldak (output) dstb (output) r/w (output) hldrq (input) astb (output) ad0 to ad15 (i/o) d0 to d15 (input or output) <55> <61> <62> <57> <54> <54> <56> <58> <56> <60> <59> note uben (output), lben (output) remark broken line indicates high impedance.
m pd703003 70 data sheet u12261ej2v1ds00 (8) interrupt timing parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. nmi high-level width <63> t wnih 500 500 ns nmi low-level width <64> t wnil 500 500 ns intpn high-level width <65> t with n = 110 to 113, 120 to 123, 3t + 10 3t + 10 ns 130 to 133, 140 to 143 intpn low-level width <66> t witl n = 110 to 113, 120 to 123, 3t + 10 3t + 10 ns 130 to 133, 140 to 143 remark t = t cyk remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 nmi (input) <63> <64> intpn (input) <65> <66>
71 m pd703003 data sheet u12261ej2v1ds00 [memo]
m pd703003 72 data sheet u12261ej2v1ds00 (9) csi timing (1/2) (a) master mode (i) timing of csi0 to csi2 parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. sckn cycle <67> t cysk1 output 160 120 ns sckn high-level width <68> t wskh1 output 0.5t cysk1 C 20 0.5t cysk1 C 20 ns sckn low-level width <69> t wskl1 output 0.5t cysk1 C 20 0.5t cysk1 C 20 ns sin setup time (to sckn - ) <70> t ssisk1 50 50 ns sin hold time (from sckn - ) <71> t hsksi1 00ns son output delay time (to sckn ) <72> t dskso1 18 18 ns son output hold time (from sckn - ) <73> t hskso1 0.5t cysk1 C 5 0.5t cysk1 C 5 ns remark n = 0 to 2 (ii) timing of csi3 parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. sck3 cycle <67> t cysk3 output r l = 1.5 k w 500 500 ns sck3 high-level width <68> t wskh3 output c l = 50 pf 0.5t cysk3 C 150 0.5t cysk3 C 150 ns sck3 low-level width <69> t wskl3 output 0.5t cysk3 C 70 0.5t cysk3 C 70 ns si3 setup time (to sck3 - ) <70> t ssisk3 100 100 ns si3 hold time (from sck3 - ) <71> t hsksi3 50 50 ns so3 output delay time (to sck3 ) <72> t dskso3 r l = 1.5 k w 150 150 ns so3 output hold time (from sck3 - ) <73> t hskso3 c l = 50 pf t wskh3 t wskh3 ns remark r l and c l are the load resistance and load capacitance of the output line for sck3 and so3. (b) slave mode (i) timing of csi0 to csi2 parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. sckn cycle <67> t cysk2 input 160 120 ns sckn high-level width <68> t wskh2 input 50 30 ns sckn low-level width <69> t wskl2 input 50 30 ns sin setup time (to sckn - ) <70> t ssisk2 10 10 ns sin hold time (from sckn - ) <71> t hsksi2 10 10 ns son output delay time (to sckn ) <72> t dskso2 45 45 ns son output hold time (from sckn - ) <73> t hskso2 t wskh2 t wskh2 ns remark n = 0 to 2
73 m pd703003 data sheet u12261ej2v1ds00 (9) csi timing (2/2) (ii) timing of csi3 parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. sck3 cycle <67> t cysk4 input 500 500 ns sck3 high-level width <68> t wskh4 input 100 100 ns sck3 low-level width <69> t wskl4 input 180 180 ns si3 setup time (to sck3 - ) <70> t ssisk4 100 100 ns si3 hold time (from sck3 - ) <71> t hsksi4 50 50 ns so3 output delay time (to sck3 ) <72> t dskso4 r l = 1.5 k w 150 150 ns so3 output hold time (from sck3 - ) <73> t hskso4 c l = 50 pf t wskh4 t wskh4 ns remark r l is the load resistance and c l is the load capacitance of the output line for sck3 and so3. sckn (i/o) sin (input) son (output) <67> <69> <68> <70> <71> <72> <73> input data output data remarks 1. broken line indicates high impedance. 2. n = 0 to 3
m pd703003 74 data sheet u12261ej2v1ds00 (10) rpu timing parameter symbol conditions 25-mhz version 33-mhz version units min. max. min. max. ti1n high-level width <74> t wtih 3t + 10 3t + 10 ns ti1n low-level width <75> t wtil 3t + 10 3t + 10 ns tclr1n high-level width <76> t wtch 3t + 10 3t + 10 ns tclr1n low-level width <77> t wtcl 3t + 10 3t + 10 ns remark t = t cyk ti1n (input) <74> <75> tclr1n (input) <76> <77> remark n = 1 to 4
75 m pd703003 data sheet u12261ej2v1ds00 a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v) parameter symbol conditions 25-mhz version 33-mhz version units min. typ. max. min. typ. max. resolution 10 10 bit total error note 1 4.5 v av ref1 av dd 0.55 0.55 %fsr 3.5 v av ref1 av dd 0.7 0.7 %fsr quantization error 1/2 1/2 lsb conversion time t conv 4.5 v av ref1 av dd 48 60 t cyk 3.5 v av ref1 av dd 48 60 t cyk sampling time t samp 4.5 v av ref1 av dd 810t cyk 3.5 v av ref1 av dd 810t cyk zero scale error note 1 4.5 v av ref1 av dd 3.0 4.5 3.0 4.5 lsb 3.5 v av ref1 av dd 3.0 5.5 3.0 5.5 lsb full scale error note 1 4.5 v av ref1 av dd 1.5 2.5 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 1.5 4.5 lsb nonlinearity error note 1 4.5 v av ref1 av dd 1.5 3.5 1.5 3.5 lsb 3.5 v av ref1 av dd 1.5 4.5 1.5 4.5 lsb analog input v ian C0.3 av dd C0.3 av dd v voltage note 2 +0.3 +0.3 reference voltage av ref1 3.5 av dd 3.5 av dd v av ref1 current ai ref1 1.2 3.0 1.2 3.0 ma av dd power supply ai dd 2.3 6.0 2.3 6.0 ma current notes 1. does not include quantization error. 2. when v ian = 0, the conversion result becomes 000h. when 0 < v ian < av ref1 , conversion has 10-bit resolution. when av ref1 v ian av dd , the conversion result becomes 3ffh.
m pd703003 76 data sheet u12261ej2v1ds00 d/a converter characteristics (t a = C40 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v) parameter symbol conditions 25-mhz version 33-mhz version units min. typ. max. min. typ. max. resolution 8 8 bit total error load condition: 2 m w , 30 pf 0.8 0.8 % av ref2 = v dd av ref3 = 0 load condition: 2 m w , 30 pf 1.0 1.0 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd load condition: 4 m w , 30 pf 0.6 0.6 % av ref2 = v dd av ref3 = 0 load condition: 4 m w , 30 pf 0.8 0.8 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd settling time load condition: 2 m w , 30 pf 10 10 m s output resistance ro 10 10 k w av ref2 input voltage av ref2 0.75 v dd v dd 0.75 v dd v dd v av ref3 input voltage av ref3 0 0.25 v dd 0 0.25 v dd v av ref2 to av ref3 r airef dacs0, dacs1 = 55h 2 5 2 5 k w resistance value
77 m pd703003 data sheet u12261ej2v1ds00 17. package drawings 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a 16.0 0.2 0.630 0.008 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 16.0 0.2 0.630 0.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009 0.002 p100gc-50-7ea-3 k 1.0 0.2 0.039 +0.009 ?.008 l 0.5 0.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 +0.05 ?.04 +0.03 ?.07 q 0.125 0.075 0.005 0.003 r s 1.7 max. 5 5 5 5 0.067 max. +0.001 ?.003 p 1.45 0.05 0.057 +0.003 ?.002 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 1 25 26 50 100 76 75 51 m s s c q r k m l p g f a b d j hi n s detail of lead end
m pd703003 78 data sheet u12261ej2v1ds00 18. recommended soldering conditions the m pd703003 should be soldered and mounted under the following recommended conditions. for the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 18-1. soldering conditions soldering method soldering conditions symbol infrared reflow ir35-107-2 vps vp15-107-2 partial heating note exposure limit after dry-pack is opened. storage conditions: temperature of 25 c and relative humidity of 65% or less. caution do not use different soldering methods together (except for partial heating). package peak temperature: 235 c, reflow time: 30 seconds or below (210 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) package peak temperature: 215 c, reflow time: 40 seconds or below (200 c or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) pin temperature: 300 c or below, time: 3 seconds or below (per side of device)
79 m pd703003 data sheet u12261ej2v1ds00 [memo]
m pd703003 80 data sheet u12261ej2v1ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
81 m pd703003 data sheet u12261ej2v1ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd703003 related documents m pd703003a, 703004a, 703025a data sheet (under preparation) m pd70f3003 data sheet (u12036e) m pd70f3003a, 70f3025a data sheet (u13189e) v850 family, instruction table (u10229j) note note japanese version the related documents indicated in this publication may include preliminary version. however, preliminary versions are not marked as such. v850 family and v853 are trademarks of nec corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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